NMI=0, FOFCE=0, FDZCE=0, FIXC=0, IRQ=0, FDZC=0, FIXCE=0, FIOC=0, CWBEE=0, FOFC=0, FIDCE=0, CWBER=0, FIDC=0, FUFC=0, FIOCE=0, DHREQ=0, FUFCE=0
Interrupt Status and control Register
| RESERVED | no description available |
| IRQ | Normal Interrupt Pending 0 (0): No pending interrupt 1 (1): Due to the ETB counter expiring, a normal interrupt is pending |
| NMI | Nonmaskable Interrupt Pending 0 (0): No pending NMI 1 (1): Due to the ETB counter expiring, an NMI is pending |
| DHREQ | Debug Halt Request Indicator 0 (0): No debug halt request 1 (1): Debug halt request initiated |
| CWBER | Cache write buffer error status 0 (0): No error 1 (1): Error occurred |
| RESERVED | no description available |
| FIOC | FPU invalid operation interrupt status 0 (0): No interrupt 1 (1): Interrupt occurred |
| FDZC | FPU divide-by-zero interrupt status 0 (0): No interrupt 1 (1): Interrupt occurred |
| FOFC | FPU overflow interrupt status 0 (0): No interrupt 1 (1): Interrupt occurred |
| FUFC | FPU underflow interrupt status 0 (0): No interrupt 1 (1): Interrupt occurred |
| FIXC | FPU inexact interrupt status 0 (0): No interrupt 1 (1): Interrupt occurred |
| RESERVED | no description available |
| FIDC | FPU input denormal interrupt status 0 (0): No interrupt 1 (1): Interrupt occurred |
| RESERVED | no description available |
| CWBEE | Cache write buffer error enable 0 (0): Disable error interrupt 1 (1): Enable error interrupt |
| RESERVED | no description available |
| FIOCE | FPU invalid operation interrupt enable 0 (0): Disable interrupt 1 (1): Enable interrupt |
| FDZCE | FPU divide-by-zero interrupt enable 0 (0): Disable interrupt 1 (1): Enable interrupt |
| FOFCE | FPU overflow interrupt enable 0 (0): Disable interrupt 1 (1): Enable interrupt |
| FUFCE | FPU underflow interrupt enable 0 (0): Disable interrupt 1 (1): Enable interrupt |
| FIXCE | FPU inexact interrupt enable 0 (0): Disable interrupt 1 (1): Enable interrupt |
| RESERVED | no description available |
| FIDCE | FPU input denormal interrupt enable 0 (0): Disable interrupt 1 (1): Enable interrupt |